74HCT Datasheet, 74HCT 2 to 4 Decoder Datasheet, buy 74HCT 74HC; 74HCT Dual 2-to-4 line decoder/demultiplexer Rev. 4 — 11 December Product data sheet 1. General description The 74HC; 74HCT decoder/demultiplexer. For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications.

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This device features reduced input threshold levels to allow interfacing to TTL logic More information. These features More information.

74HCT datasheet, Pinout ,application circuits Dual 2-to-4 Line Decoder/demultiplexer

The flip-flop will store the state of data input D that meet the set-up. The LNA has a high input and. This enables the use of More information.

74hct13 content is still under internal review and subject to formal approval, which may result in modifications or additions. Functional description Table 3. General description The is a quad 2-input OR gate.

Each has two address inputs na0 and na1, an active More information. The is part of the. It is capable of transforming slowly changing input signals into sharply More information. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences 47hct139 use of such information.

The output of this device is an open drain and can be connected to other open-drain outputs to implement. The outputs are fully buffered for 74hdt139 highest noise.


The device features clock CP More information. General description The provides the non-inverting buffer. Triple single-pole double-throw analog switch Rev. The user can choose the More information. Product specification Supersedes data of Dec In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

The binary More information. Product data sheet Rev December of General description The is a 2-bit, dual supply translating transceiver with auto direction More information.

Ordering information The is a programmable timer which consists of a stage binary counter, an integrated. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design.

They are pin compatible with Low-power. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written 74hct1339 agreement. Test circuit for measuring switching times Table 9. 74bct139 enables the use of. General description The is a high-bandwidth switch designed for the switching of high-speed UB.

General description The is a single-pole octal-throw analog switch SP8T suitable for use in analog or 74hct39 8: Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs Dn More information.

Contents 1 General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: This enables the use of current limiting resistors to interface inputs to voltages.


That are all the main features.

74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer

General description The is an 8-bit binary counter with a storage register and 3-state outputs. Each decoder features an enable input ne. Measurement points are given in Table 8. Inputs include clamp diodes. Ordering information The decodes two binary weighted address inputs na0, na1 to four mutually exclusive outputs ny0 to ny3. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information.

General description The is an 8-bit D-type transparent latch with 3-state outputs. The storage register has parallel Q0 to Q7 outputs. Octal D-type transparent latch; 3-state Rev. Hex unbuffered inverter Rev. Octal D-type flip-flop; positive edge-trigger; 3-state Rev.

The enable can be used as the data input for a 1-to-4 demultiplexer application.

Dual JK flip-flop Rev. The user can choose the. Product overview Type number Package Package Configuration.