CS2354 ADVANCED COMPUTER ARCHITECTURE LECTURE NOTES PDF

CS2354 ADVANCED COMPUTER ARCHITECTURE LECTURE NOTES PDF

Dear students here we provide notes for Anna university 6TH sem Subject CS ADVANCED COMPUTER ARTCHITECTURE notes pdf. you can download. ADVANCED COMPUTER ARCHITECTURE LECTURE NOTES ANNA UNIVERSITY ADVANCED COMPUTER ARCHITECTURE LECTURE. CS ADVANCED COMPUTER ARCHITECTURE. UNIT – I. 2 Marks. is ILP .. Statically scheduled. – Dynamically scheduled (see previous lecture).

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Advanced Computer Architecture CS notes – Annauniversity lastest info

Various types of Dependences in ILP. There are three different types of dependences: There are two types of name dependences between an instruction i that precedes instruction j in program order: The presence of the dependence indicates the potential for a ,ecture, but the actual hazard and the length of any stall is a property of the pipeline.

The second condition simply states that one instruction is dependent on another if there exists a chain of dependences of the first type between the two instructions. Share it with your friends. In general, there are two constraints imposed by control dependences: This difference is critical to understanding how cs254 parallelism can be exploited. Dependences are a property of programs.

CS Advanced Computer Architecture Lecture Notes – SEC Edition

noes Static Technique — Software Dependent 2. CS Name of the subject: This dependence chain can be as long as the entire program. A control dependence determines the ordering of an instruction, i, with respect to a branch instruction so that the instruction i is executed in correct program order.

Data Dependence and Hazards: Both anti-dependences and output dependences are name dependences, as opposed to true data dependences, since archihecture is no value being transmitted between the instructions.

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Every instruction, except for those in the first basic block of the program, is control dependent on some set of branches, and, in general, these control dependences must be preserved to preserve program order.

Note for Advanced Computer Architecture – ACA by Rajib Swain

Register renaming can be done either statically by a compiler or dynamically by the hardware. Here is a simple example of a loop, which adds two element arrays, that is completely parallel: Text from page-2 Lecture Plan Subject Code: Whether a given dependence results in an actual hazard being detected and whether that hazard actually causes a stall are properties of the pipeline organization.

Instruction-level parallelism ILP is the potential overlap the execution of instructions using pipeline concept to improve performance of the system. For archihecture, in the code segment: The various techniques that are used to increase amount of parallelism are reduces the impact of data and control hazards and increases processor ability to exploit parallelism There are two approaches to exploiting ILP.

Nptes Plan Subject Code: An instruction that is control dependent on a branch cannot be moved before the branch so that its execution is no longer controlled by the branch.

If two instructions are parallel, they can execute simultaneously in a pipeline without causing any stalls. Text from page-1 Lecture Plan Subject Code: Executing the instructions simultaneously will cause a processor with pipeline interlocks to detect a hazard and stall, thereby reducing or eliminating the overlap.

Text from page-3 Lecture Plan Subject Code: Name Dependences The name dependence occurs when two instructions use the same register or memory location, called a name, but there is no flow of data between the instructions associated with that name. The original ordering must be preserved to ensure that i reads the correct value.

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The importance of the data dependences is that a dependence 1 indicates the possibility of a hazard, 2 Determines the order in which results must be calculated, and 3 Sets an upper bound on how much parallelism can possibly be exploited.

Dynamic Technique — Hardware Computfr Technique Forwarding and bypassing Delayed branches and simple branch scheduling Basic dynamic scheduling scoreboarding Dynamic scheduling with renaming Dynamic branch prediction Issuing multiple instructions per cycle Speculation Dynamic memory disambiguation Loop unrolling Basic compiler pipeline scheduling Compiler dependence analysis Software pipelining, trace scheduling Compiler speculation Reduces Potential cimputer hazard stalls Control hazard stalls Data hazard stalls from true dependences Data hazard stalls and stalls from anti dependences and output dependences Control stalls Ideal CPI Data hazard and control hazard stalls Data hazard stalls with memory Control hazard aevanced Data hazard stalls Ideal CPI, data hazard stalls Ideal CPI, data hazard stalls Ideal CPI, data, control stalls 1.

If two instructions are dependent they are not parallel and must be executed in order. Touch here to read. Advancsd from page-4 Lecture Plan Subject Code: To exploit instruction-level parallelism, determine which instructions can be executed in parallel.